Initialization

During initialization, status codes are used to show the current step and indicate initialization problems. Three methods are used:

Initialization Steps
LED Status Codes
Beep Codes

Initialization Steps

Initialization Routine	Description
Test the PCI	Data path test in PCI configuration space. Read the Vendor ID and Device ID fields from the PCI Configuration Header of the PCI/ISA Bridge chip. Check against expected values.
Size the Bcache	Init the CPU Scache and then determine if Bcache is present. If present, determine Bcache size and speed. If not present, set CPU to make all off-chip references to main memory.
Size memory	Size the main memory on a bank-per-bank basis. The IIC ROM is read from each DIMM. Banks with mismatched DIMMs will cause an error beep code
Configure memory	Configure memory so the large banks are in low memory and the smaller banks are in high memory.
Test memory	Test memory data paths, address lines, and memory cells.
Initialize memory	Initialize all of configured memory with zeroes. If the Bcache is present, it is flooded to force the highest tags out of Bcache and into memory.
Load the console firmware	Verify the data path and checksum and then load the system console firmware from the flashROM into memory at the PAL base address.
Initialize the system interface	The system CPU/system interface consists of the PYXIS chip and the PCI/ISA bridge chip. Zero the window base registers, init the PYXIS, and zero the IRQ.
Set up the mailbox.	Build the mailbox containing system information to leave in memory for the console firmware and/or the OS.

LED Status Codes

When power is turned on, SROM code initializes the CPU, core logic, and memory. After successful initialization, the SROM code loads and starts the AlphaBIOS firmware. The SROM powerup status codes, visible in LEDs on the MLB, are divided into three main categories:

FF to F0 Fatal error codes (powerup program halts with no further activity).
EF to E0 Error codes (may not prevent AlphaBIOS from starting).
DF to CC Status codes (identify current process in the powerup sequence).

Powerup Codes		Description
LEDs	Hex	Description
	FF	No Scache bits set in SC_CTL register.
	FA	No usable memory detected.
	F9	System initialization failure.
	F8	PCI data path error.
	F5	Bcache data path error.
	F4	Bcache address line error.
	F3	Bcache cell error.
	F1	FlashROM data path read error.
	E5	Memory data path error.
	E4	Memory address line error.
	E0	FlashROM checksum error.
	DE	Init the CPU/system interface.
	DC	Sizing the scache.
	DB	Testing the PCI data path.
	DA	Bcache sizing in progress.
	D9	Memory sizing in progress.
	D8	Memory configuration in progress.
	D7	Memory test initialization in progress.
	D6	Bcache bits test in progress.
	D5	Memory bits test in progress.
	D4	Bcache address test in progress.
	D3	Memory address test in progress.
	D2	Bcache cell test in progress.
	D0	Initialize all of memory.
	CF	Console firmware loading.
	CE	Re-init the CPU/system interface (if inited before).
	CD	SROM code execution complete, transfer control to the console firmware.

Beep Codes

Beep Code	Description
1-2-4	SROM code detected a memory error.
1-3-3	No memory was detected; or there was memory, but during testing it failed and was marked unavailable.
1-1-4	Bad flashROM data path (manufacturing data pattern did not match the expected pattern, or there was a checksum error).