Address Configuration

This section covers the following topics:

• Address space overview.
• PCI address space.
• CPU address space.

Address Space Overview

The EV5 address space is divided into two regions using physical address bit [39]. If the address space is clear, then the CPU is accessed to the cached memory space. If it is set, then the accesses are not cached. The uncached space is used to access memory-mapped I/O devices. Mailboxes are not supported. The uncached space contains the CSRs, uncached memory access (for diagnostics), and the PCI address space. The PCI defines three physical address spaces:

1. 64-bit PCI memory space
2. 4-GB PCI I/O space
3. 256 byte per device PCI configuration space

In addition to the three PCI address spaces, the CPU's uncached space also is used to generate PCI Interrupt Acknowledge and Special Cycles.

The system can perform two modes of addressing: byte/word disabled (0) and byte/word enabled (1). The mode is controlled by bit 0 (IOA_BEN) of the PYXIS_CTRL1 CSR.

Physical Address Map with Byte/Word Mode Disabled

Physical Address Map with Byte/Word Mode Enabled

The CPU has visibility to the complete address space. It can access cached memory, CSRs as well as all the PCI memory, I/O and configuration regions. See Figure 3-1.

The PCI devices have a restricted view of the address space. They can access any PCI device through the PCI memory or PCI I/O space; but they have no access to the PCI configuration space. Furthermore, the system restricts access to the system memory (for DMA operations) through five, programmable "windows" (that is, memory regions) in the PCI memory space. See the figure.

DMA access to the system memory is achieved through "windows" in one of three ways:

1. Directly using the Monster Window with Dual Address Cycles where PCI address <33:0> equals memory address <33:0>.
2. Directly mapped by concatenating an offset to a portion of the PCI address.
3. Virtually through a scatter/gather translation map.

The scatter/gather map allows any 8-KB PCI memory address region (page) to be re-directed to any 8-KB cached memory page, as shown below.

PCI address Space

The system generates 32-bit PCI addresses but accepts both 64-bit address (double address cycle [DAC] ) cycles and 32-bit PCI address (single address cycle [SAC] ) cycles. The process of accessing main memory is as outlined next:

• Window [4], the Monster Window, gives full access to main memory. It is accessed by DAC only with PCI address<40> set. Memory address<33:0> equals PCI address <33:0>.
• Window [3] can be either DAC or SAC, but not both. If it is DAC, PCI address <63:40> must be zero, PCI address <39:32> must match the DAC register, and PCI address <31:0> must hit in Window [3].
• Windows [2:0] are SAC-only.

When the system is initialized by the SROM code, the windows are configured as follows:

CPU Address Space

The following figure shows an overview of the mapping of the 40-bit processor physical address space into memory and I/O space addresses:

     39      34 33 32 31
+---+---+---+--+--+--+--+------------------------------+
|   |   |SBZ|  |  |  |  |                              |
+---+---+---+--+--+--+--+------------------------------+
      /\- - - - - - - - - +--------+
      |      0   0  x  x  |        |  8-GB Cached
      |                   +--------+      Memory
      |                   |        |
 <39>=0= Cached           |Reserved|
      |  Memory           |        |
      |  Space            |        |
      |                   |        |
      |                   |        |
      \/                  |        |
      - - - - - - - - - - +--------+ - - - - - - 
      /\     0   x  x  x  |        | 80.0000.0000   /\
      |                   |        |                 |
      |                   | 16-GB   |                 |
      |                   |        |            PCI Memory
      |                   |        |            Sparse Space
      |                   |        |            704-MB Max
      |                   +--------+                 |
      |      1   0  0  x  |  4-GB   | 84.0000.0000    |
 <39>=1= Uncached         |        |                 |
      |  I/O Space        +--------+                 |
      |      1   0  1  0  |  2-GB   | 85.0000.0000   \/
      |                   +--------+ - - - - - - -- - -
      |      1   0  1  1  |        | 85.8000.0000 PCI Sparse
      |                   |        |              I/O 64-MB
      |                   +--------+
      |      1   1  0  x  |        | 86.0000.0000 PCI Dense
      |                   |        |              Memory 4-GB
      |                   +--------+
      \/     1   1  1  x  |        | 87.0000.0000 PCI Config
      - - - - - - - - - - +--------+              CSRs, and
                                                    flashROM

The preceding figure shows how the CPU address map translates to the PCI address space as well as how the PCI accesses the CPU memory space through DMAs. Notice how the PCI memory space is double-mapped by dense and sparse space. The rationale behind the CPU I/O address map is as follows: (1) To provide 4 GB of dense space to completely map the 32-bit PCI memory space and (2) To provide abundant PCI sparse memory space since sparse-space has byte granularity and is the safest memory-space to use (for example, no prefetching). Furthermore, the larger the space, the less likely software will need to dynamically relocate the sparse space segments. The main problem with sparse space is that it wastes CPU address space (for example, 16 GB of CPU address space maps to 512 MB of PCI sparse space). The system provides three PCI memory, sparse-space regions, allowing 704 MB of total sparse memory space. The three regions are relocatable through the HAE_MEM CSR, and the simplest configuration allows for 704 MB of contiguous memory space. (a) 512 MB region, which may be located in any naturally aligned 512-MB segment of the PCI memory space. This region may be sufficient for software. (b) 128-MB regions, which may be located on any naturally aligned 128-MB segment of the PCI memory space. (c) 64-MB region, which may be located on any naturally aligned 64-MB segment of the PCI memory space. Limit the PCI I/O space to sparse space: although the PCI I/O space can handle 4 GB, the Pentium chip can access only 64 KB. Consequently, most, if not all, PCI devices will not exceed 64 KB for the foreseeable future. The system provides 64 MB of sparse I/O space because the hardware decode is faster. The system provides two PCI IO sparse-space regions: region A, which is 32 MB and is fixed in PCI segment 0-32 MB; and region B, which is also 32 MB, but is relocatable using the HAE_IO register.